Composite printing

ABSTRACT

Systems and techniques for printing substrates. In one implementation, a method includes patterning a substrate with a substantially arbitrary arrangement of features by introducing irregularity into a repeating array of features.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a divisional application of and claims priority toU.S. application Ser. No. 10/688,306, filed on Oct. 17, 2003, thecontents of which are incorporated herein by reference.

BACKGROUND

This disclosure relates to the printing of substrates.

Various lithographic techniques can be used to print patterns such asthose that define integrated circuits in microelectronic devices. Forexample, optical lithography, e-beam lithography, UV and EUVlithography, x-ray lithography and imprint printing techniques can allbe used to form micron- and submicron-sized features.

DESCRIPTION OF DRAWINGS

FIG. 1 is a top view of a wafer.

FIG. 2 is a sectional view of a portion of a layout piece on a waferduring processing.

FIG. 3 is a top view of a layout piece after exposure and development toform a two-dimensional array of features.

FIG. 4 is a sectional view of the layout piece of FIG. 3.

FIGS. 5, 6, and 7 are sectional views along the same plane as FIG. 4after additional processing.

FIG. 8 shows a top view of a layout piece after exposure and developmentto form a pattern.

FIG. 9 shows a sectional view of the layout piece of FIG. 8.

FIGS. 10 and 11 are sectional views along the same plane as FIG. 9 afteradditional processing.

FIG. 12 shows a top view of a layout piece after removal of asacrificial layer.

FIG. 13 shows a sectional view of the layout piece of FIG. 12.

FIG. 14 shows a composite optical lithography system.

FIG. 15 shows an example patterning system in the composite opticallithography system of FIG. 14.

Like reference symbols in the various drawings indicate like elements.

DETAILED DESCRIPTION

FIG. 1 shows a top view of a wafer 100. Wafer 100 is a semiconductorwafer being processed to form at least one integrated circuit devicesuch as a microprocessor, a chipset device, or a memory device. Forexample, wafer 100 can be used to form a collection of SRAM memorydevices. Wafer 100 can include silicon, gallium arsenide, or indiumphosphide. Wafer 100 includes an array of die portions 105. Wafer 100can be diced or otherwise processed to form a collection of dice thatcan be packaged to form individual integrated circuit devices. Each dieportion 105 includes one or more layout pieces 110. A layout piece 110is a section of a die portion 105 that includes a pattern. The patterndefined in a layout piece 110 generally contributes to the function ofintegrated circuit devices formed from die portions 105.

FIG. 2 is a sectional view of a portion of layout piece 110 on wafer100. At the processing stage illustrated in FIG. 2, layout piece 110includes a substrate 205, a pattern layer 210, a sacrificial layer 215,and a printing layer 220. Substrate 205 can be the base wafer or anotherlayer formed during previous processing. Pattern layer 210 is theportion of layout piece 110 that is to be patterned. Pattern layer 210can be patterned to form all or a portion of a microelectronic device.Pattern layer 210 can be, e.g., an electrical insulator such as silicondioxide or nitride, a semiconducting material such as p- or n-dopedsilicon, or a conducting layer such as copper or aluminum. Sacrificiallayer 215 is a temporary layer that can be selectively removed frompattern layer 210. Sacrificial layer 215 can be an interlayer dielectric(ILD) such as a silicon oxide or nitride. Printing layer 220 is amaterial that is sensitive to one or more techniques for printingpatterns. For example, printing layer 220 can be a positive or negativephotoresist. The following description assumes printing layer 220 to bea positive photoresist.

Resist layer 220 can be exposed and developed to form a pattern. FIG. 3is a top view and FIG. 4 is a sectional view of layout piece 110 afterexposure and development to form a two-dimensional array 300 ofrepeating features 305. Features 305 repeat in array 300 in that,excepting manufacturing defects and other irregularities in individualfeatures 305, array 300 includes a repetitive order or arrangement ofindividual features 305. Array 300 can be rectangular or square with alength 310 and a width 315 that occupies all or a portion of layoutpiece 110. Features 305 in array 300 have a pitch 320. The pitch offeatures is the smallest spatial periodicity of the features. Forexample, contact pitch 320 is the sum of the width 325 of a contact 305and the shortest distance 330 to the next nearest contact 305. Only asingle pair of contacts 305 need be at pitch 320. Thus, the separationdistance and width of contacts 305 can vary (e.g., in the horizontal andvertical directions) and array 300 can still have pitch 320.

Features 305 can be formed using any of a number of differentlithographic techniques such as e-beam lithography, interferencelithography, and optical lithography using phase-shifting masks andoptical proximity correction techniques. These lithographic techniquescan involve the exposure of wafer 100 using an interference pattern. Forexample, features 305 can be formed using interference lithography byexposing resist 220 using two orthogonal sets of interfering laser beamswith a wavelength λ₁ to form the array of features with pitch 320approaching ½λ₁. The orthogonal sets can be generated by splitting asingle source four ways using a pyramidal prism and interfering thereflections from two orthogonal pairs of opposing pairs of mirrors. Theorthogonal pairs can illuminate a substrate at different angles ofillumination or the orthogonal pairs can illuminate a substrate at thesame angle of illumination. Illuminating at the same angle can impartthe substrate with the same pitch in both, orthogonal, directions.Alternatively, the orthogonal sets can be generated by double exposingresist 220 after wafer 100 is subject to a 90° rotation in a traditionalinterferometric lithography system.

Features 305 can display features characteristic of the lithographictechnique used to form features 305. For example, when features 305 areformed using interference lithography, features 305 can be formed with adefinition characteristic of interference lithography and a pitchapproaching ½λ₁ with minimal feature distortion of the type that arisesdue to imperfections in projection printing systems and techniques. Forexample, features 305 can be formed without imperfections that arise dueto the use of a mask, lenses, projection optics, and/or thebackscattering of electrons. Features 305 can also show the influence ofthe relatively large depth of focus provided by interferometriclithography techniques. For example, the relatively large depth of focuscan provide precise control of the dimensional characteristics offeatures, especially relative to the control provided by optical systemsin which high numerical apertures limit both the depth of field and theability to print real world substrates that are not ideally flat.

FIGS. 5, 6, and 7 are sectional views along the same plane as FIG. 4after additional processing. In particular, FIG. 5 shows layout piece110 after an etch has defined cavities 505 in sacrificial layer 215. Forexample, cavities 505 can be defined using a dry plasma etch. Cavities505 can inherit the character of features 305 that are characteristic ofthe lithographic technique used to form features 305. For example, whenfeatures 305 are exposed using interference lithography, cavities 505can inherit the definition characteristic of interference lithographywhere minimal pitch approaches ½λ₁ with minimal feature distortion ofthe type that arises due to imperfections in projection printing systemsand techniques. Cavities 505 can be generally cylindrical with theiraxes oriented perpendicular to the plane of wafer 100. Cavities 505 canbe defined to have substantially the same pitch 320 as features 305.Cavities 505 can have diameters smaller, larger, or substantially thesame as the diameters of features 305, depending on the etch processselected to define cavities 505.

FIG. 6 shows layout piece 110 after resist 220 has been stripped. FIG. 7shows layout piece 110 after a new resist layer 705 has been formedabove sacrificial layer 215. Resist layer 705 can either cap or fillcavities 505 of sacrificial layer 215. Resist layer 705 can be formed,e.g., by spin coating photoresist on wafer 100.

FIG. 8 shows a top view and FIG. 9 shows a sectional view of layoutpiece 110 after resist layer 705 has be exposed and developed to form aFIG. 805. FIG. 805 can be arbitrarily shaped in that FIG. 805 need notinclude a repetitive order or arrangement. FIG. 805 is aligned with thetwo-dimensional array of cavities 505 to either expose (for example, at810) or cover (for example, at 815) individual cavities 505.

FIG. 805 can be formed with a length 820 and a width 825 that occupiesall or a portion of layout piece 110. FIG. 805 can include elements witha pitch 830. Pattern element pitch 830 is the sum of the width 835 of anelement 840 and the shortest distance 845 to the next nearest element850. Only a single pair of elements in FIG. 805 need be at pitch 830.Thus, the separation distance and width of elements can vary, and FIG.805 can still have pitch 830. Pitch 830 can be two or more times aslarge as contact pitch 320.

Since pattern pitch 830 can be relatively larger than contact pitch 320,FIG. 805 can be formed using lithographic systems and techniques thathave a lower resolution than the systems and techniques used to formfeatures 305. For example, if features 305 are formed using aninterferometric lithography system with a wavelength λ₁, then FIG. 805can be formed using an optical lithography system with a wavelengthlarger than λ₁. As another example, FIG. 805 can be formed using atraditional binary optical lithography system, or other lithographicsystems such as imprint and e-beam lithographic systems capable ofachieving the lower resolution.

The exposure or shielding of cavities 505 by FIG. 805 can be used tointroduce irregularity into the repeating array of cavities 505 afterhardening of resist 705. In other words, the arbitrary shape of FIG. 805can be used to stop the periodic reoccurrence of features in layoutpiece 110.

FIGS. 10 and 11 are sectional views along the same plane as FIG. 8 afteradditional processing. In particular, FIG. 10 shows layout piece 110after an etch has defined cavities 1005 in pattern layer 210. Forexample, cavities 1005 can be defined using a dry plasma etch. Cavities1005 can inherit, by way of cavities 505, the character of features 305that are characteristic of the lithographic technique used to formfeatures 305. For example, when features 305 are exposed usinginterference lithography, cavities 1005 can inherit, by way of cavities505, the definition characteristic of interference lithography withminimal feature distortion of the type that arises due to imperfectionsin projection printing systems and techniques at a pitch approaching λ₁.Cavities 1005 can be generally cylindrical, with their axes orientedperpendicular to the plane of wafer 100. Cavities 1005 can be defined tohave substantially the same pitch 320 as features 305. Cavities 1005 canhave diameters smaller, larger, or substantially the same as thediameters of cavities 505.

FIG. 11 shows layout piece 110 after resist 705 has been stripped toexpose previously covered cavities 505. FIGS. 12 shows a top view andFIG. 13 shows a sectional view of layout piece 110 after sacrificiallayer 215 has been removed. Sacrificial layer 215 can be removed bychemical mechanical polishing (CMP) or by etching. After removal ofsacrificial layer 215 and the exposure of cavities 1005, pattern layer210 in layout piece 110 includes a collection of pattern features 1205.Pattern features 1205 can be used in a functional design layout of amicroelectronic device. Pattern features 1205 can have pitch 320 that islimited by the pitch available from the lithographic technique used toform contacts 305. Moreover, depending upon the geometry of resist FIG.805, pattern features 1205 can also have an arbitrary arrangement inpattern layer 210 since, after irregularity is introduced into repeatingarray 300, the impact of at least some of the small pitch features 305upon wafer 100 has been eliminated.

Such composite patterning can prove advantageous. For example, a singlelayout piece can be patterned with features using a higher resolutionsystem or technique and the functional impact of those features can bemodified or even eliminated using a lower resolution system ortechnique. For example, older, typically lower resolution, equipment canbe used to modify the impact of higher resolution features, providingincreased lifespans to the older equipment. Patterning cost can bedecreased by devoting high resolution systems to the production of highresolution features while using less expensive, lower resolution systemsfor the modification of the impact of those high resolution features.For example, high resolution but relatively inexpensive interferometricsystems can be combined with relatively inexpensive low resolutionsystems to produce high quality, high resolution patterns without largecapital investments. Since the arrangement of patterns produced usinginterferometric systems can be changed using lower resolution systems,the applicability of interferometric systems can be increased. Inparticular, interferometric systems can be used to form substantiallyarbitrary arrangements of features that are not constrained by thegeometries and arrangements of interference patterns.

FIG. 14 shows a composite optical lithography system 1400. System 1400includes an environmental enclosure 1405. Enclosure 1405 can be a cleanroom or other location suitable for printing features on substrates.Enclosure 1405 can also be a dedicated environmental system to be placedinside a clean room to provide both environmental stability andprotection against airborne particles and other causes of printingdefects.

Enclosure 1405 encloses an interference lithography system 1410 and apatterning system 1415. Interference lithography system 1410 includes acollimated electromagnetic radiation source 1420 and interference optics1425 that together provide interferometric patterning of substrates.Patterning system 1415 can use any of a number of different approachesfor patterning a substrate. For example, patterning system 1415 can bean e-beam projection system, an imprint printing system, or an opticalprojection lithography system. Patterning system 1415 can also be amaskless module, such as an electron beam direct write module, an ionbeam direct write module, or an optical direct write module.

Systems 1410, 1415 can share a common mask handling subsystem 1430, acommon wafer handling subsystem 1435, a common control subsystem 1440,and a common stage 1445. Mask handling subsystem 1430 is a device forpositioning a mask in system 1400. Wafer handling subsystem 1435 is adevice for positioning a wafer in system 1400. Control subsystem 1440 isa device for regulating one or more properties or devices of system 1400over time. For example, control subsystem 1440 can regulate the positionor operation of a device in system 1400 or the temperature or otherenvironmental qualities within environmental enclosure 1405.

Control subsystem 1440 can also translate stage 1445 between a firstposition 1450 and a second position 1455. Stage 1445 includes a chuck1460 for gripping a wafer. At first position 1450, stage 1445 and chuck1460 can present a gripped wafer to patterning system 1415 forpatterning. At second position 1455, stage 1445 and chuck 1460 canpresent a gripped wafer to interference lithography system 1410 forinterferometric patterning.

To ensure the proper positioning of a wafer by chuck 1460 and stage1445, control subsystem 1440 includes an alignment sensor 1465.Alignment sensor 1465 can transduce and control the position of thewafer (e.g., using wafer alignment marks) to align a pattern formedusing interference lithography system 1410 with a pattern formed bypatterning system 1415. Such positioning can be used when introducingirregularity into a repeating array of features, as discussed above.

FIG. 15 shows an example optical lithographic implementation ofpatterning system 1415. In particular, patterning system 1415 can be astep-and-repeat projection system. Such a patterning system 1415 caninclude an illuminator 1505, a mask stage 1510, and projection optics1515. Illuminator 1505 can include an electromagnetic radiation source1520 and an aperture/condenser 1525. Source 1520 can be the same assource 1420 or source 1520 can be an entirely different device. Source1520 can emit at the same or at a different wavelength as source 1420.Aperture/condenser 1525 can include one or more devices for collecting,collimating, filtering, and focusing the electromagnetic emission fromsource 1420 to increase the uniformity of illumination upon mask stage1510.

Mask stage 1510 can support a mask 1530 in the illumination path.Projection optics 1515 can be a device for reducing image size.Projection optics 1515 can include a filtering projection lens. As stage1445 repeatedly translates a gripped wafer for exposure by illuminator1505 through mask stage 1510 and projection optics 1515, alignmentsensor 1465 can ensure that the exposures are aligned with a repeatingarray of interferometric features to introduce irregularity into therepeating array.

A number of implementations have been described. Nevertheless, it willbe understood that various modifications may be made. For example, bothpositive and negative resists can be used for either of resist layers220, 705. Lithographic techniques that use different wavelengths can beused to process the same substrate. Substrates other than semiconductorwafers can be patterned. Accordingly, other implementations are withinthe scope of the following claims.

1. A method comprising: patterning a substrate with a substantiallyarbitrary arrangement of features by introducing irregularity into aperiodic array defined in the substrate using interference lithography.2. The method of claim 1, wherein introducing irregularity comprisesforming an arbitrary figure at a location to mask a portion of theperiodic array.
 3. The method of claim 2, wherein patterning thesubstrate further comprises etching the substrate through portions ofthe repeating array not covered by the arbitrary figure.
 4. The methodof claim 1, wherein introducing irregularity into the periodic arraycomprises introducing irregularity into a two-dimensional periodic arrayof contacts.
 5. The method of claim 1, wherein patterning the substratefurther comprises etching the substrate using the substantiallyarbitrary arrangement to direct the etching.
 6. The method of claim 1,wherein patterning the substrate further comprises patterning thesubstrate with the substantially arbitrary arrangement having a pitchapproaching one half the wavelength of electromagnetic radiation used inthe interference lithography.
 7. A method comprising: using interferencelithography to expose a substrate with an interference pattern, theinterference pattern imparting the substrate with repeating firstfeatures; and introducing irregularity into the repetition of theinterference pattern to impart a substantially arbitrary featurearrangement to the substrate.
 8. The method of claim 7, whereinintroducing irregularity comprises forming a substantially arbitraryfigure to mask some portion of the interference pattern.
 9. The methodof claim 8, further comprising patterning the substrate using thesubstantially arbitrary figure to define the substantially arbitraryfeature arrangement.
 10. The method of claim 7, wherein usinginterference lithography to expose the substrate comprises imparting, tothe substrate, first features having a pitch approaching one half thewavelength of the interference lithography electromagnetic radiation.11. A method comprising: patterning a substrate using interferencelithography, the patterning providing first features with a first pitchapproaching one half the wavelength of a patterning electromagneticradiation; and eliminating the impact of at least some of the firstfeatures on the substrate using a second lithographic techniqueproviding second features with a second pitch, the second pitch beingtwo or more times larger than the first pitch.
 12. The method of claim11, wherein patterning the substrate using interference lithographycomprises exposing the substrate with a pair of interference patterns.13. The method of claim 12, wherein exposing the substrate comprisesexposing the substrate with a substantially identical pair ofinterference patterns.
 14. The method of claim 12, wherein exposing thesubstrate comprises exposing the substrate with the pair of interferencepatterns simultaneously.
 15. The method of claim 11, wherein eliminatingthe impact of at least some of the first features on the substratecomprises patterning using a binary mask.
 16. The method of claim 11,wherein eliminating the impact of at least some of the first features onthe substrate comprises printing an arbitrary figure to mask some of thefirst features.
 17. The method of claim 16, wherein eliminating theimpact of at least some of the first features on the substrate furthercomprises etching a portion of the substrate through the first featuresnot covered by the arbitrary figure.
 18. A method comprising: usinginterference lithography to define a periodic array of features; maskingsome of the features in the periodic array; and etching a substantiallyarbitrary arrangement of features in a substrate using unmasked featuresin the periodic array as a guide.
 19. The method of claim 18, whereinusing interference lithography to define the periodic array comprisesusing interference lithography to define a periodic array of contacts.20. An apparatus comprising: an interference lithography exposure moduleto produce a first exposure resulting in an array of repeating contactsin a photosensitive media; and a second patterning module to reduceregularity of the features in the array.
 21. The apparatus of claim 20,wherein the interference exposure lithography module comprises: apyramidal beam splitter to split an electromagnetic radiation four ways;and two sets of opposing pairs of mirrors disposed to create aninterference pattern by reflecting the split electromagnetic radiation.